Shown in FIG. 1 is a prior art computer system 10 that includes a processor bus 12 coupled to a cache memory 14 and to a computer processor 16. The computer system 10 also includes a system memory 17 coupled to the processor bus 12 by a memory controller 18. Also coupled to the processor bus 12 by a PHI-host bridge 20 is a Peripheral Component Interconnect (PCI) bus 22. Coupled to the PCI bus 22 by a graphics controller 24 is a graphics monitor 26 that outputs information to a user. An Industry Standard Architecture (ISA) bus 28 also is coupled to the PCI bus 22 via a PCI-ISA bridge 30. Coupled to the ISA bus 28 are a hard drive 32 and an input device 34, such as a keyboard, mouse, or microphone, that inputs information to the computer system 10 from the user.
As computer devices have become more sophisticated and faster, it has become more difficult for the computer buses, such as the processor bus 12, to keep up with the increased rate of data flow presented by the computer devices. Whenever the processor 16 or the devices 22-36 coupled to the processor via the PCI-host bridge 20 requests access to the system memory 16, the request and accompanying data and control signals must be transmitted across the processor bus 12. As such, the performance of the entire computer system 10 can be limited by the speed of the processor bus 12, the PCI bus 22, and/or the ISA bus 28. Moreover, as the speed of computer devices continues to increase, the delays caused by sharing the resources of the processor bus 12 become more acute.
One reason for delay in computer buses, such as the processor bus 12, is that each computer bus includes one or more data lines that handle data being transmitted in both directions. For example, the processor bus 12 handles data being read from and written to the system memory 16. As a result, each time access to the system memory 16 switches from a read to a write or a write to a read, data must go completely through the processor bus 12 before data can be sent through the processor bus in the opposite direction. The time it takes to wait for the processor bus 12 to switch from one direction to the opposite direction is known as bus turn-around time and typically is at least one clock cycle of delay.
In addition to the increased speed of current computer devices, the computer buses must be able to handle the increase in the number of computer devices in current computer systems. For example, many current computer systems are provided with CD-ROM drives, local area network (LAN) connections, modems, plural microprocessors, etc. in addition to the standard computer devices shown in FIG. 1. Each computer device added to a computer system is another device that must share the same limited resources of each computer bus.
In a typical computer system, such as computer system 10, most transactions between devices are directed to the system memory 17. An additional source of delay for such memory transactions is caused by having to snoop the cache memory 14 before completing the memory transaction. Snooping refers to determining whether the cache memory 14 currently stores information in an address corresponding to a selected address of the system memory 17 being accessed (read from or written to) by the memory transaction. The processor bus 12 must be acquired before a snoop can take place and for a pipelined bus, that may take many clock cycles to occur. Only after the cache memory 14 returns an indication of whether the cache memory 14 stores information in an address corresponding to the selected address of the memory transaction can the memory transaction be completed by accessing the system memory 17.